1. Field of the Invention
This invention relates generally to communication systems. More particularly, it relates to an output impedance method calibrating a hybrid local-echo canceller and a hybrid structure implementing the same. An implementation of the invention is also compatible with a mixed-signal echo canceller.
2. Description of the Related Art
A hybrid generally refers to a device that converts a bi-directional path into two separate unidirectional paths for transmit and receive. In full-duplex communication systems, a hybrid local-echo canceller is typically used to separate incoming receive signals from outgoing transmit signals.
FIG. 1 shows a Pam-4 current-mode hybrid system 100 comprising two digital-to-analog converters (Main DAC and Replica DAC), four resistors (R1, R2, R3, and R4), and three capacitors (C1, C2, and Cbig). Cbig and ZL are off-chip components. ZL is a complex impedance that represents the channel load. The DACs, C1, C2, R1–R4, digital data and current sources are on-chip components. Exemplary Configuration 1 shows the values of these on- and off-chip components for the ideal case of ZL=50 Ohms.
The DACs produce a current based on digital data supplied at the transmit interface. The Main DAC acts as a transmitter, sending a large current ITX through the direct current (DC) blocking capacitor Cbig to the load impedance ZL. A fraction of ITX, labeled as Itx, is sent through a resistive network to the Replica DAC, which is a copy of the Main DAC connected thereto with opposite polarity. The purpose of the Replica DAC is to cancel Itx from going to the receiver. With Itx signal cancelled, only the received signal Irx is sent into the receiver.
Without calibration, the hybrid system 100 suffers from certain drawbacks as well as performance limitations. Most notably, the accuracy of the transmit signal cancellation is diminished by component mismatches, variations in the load impedance ZL, and variations in the on-chip component values.
More specifically, mismatches in absolute values between the off-chip load impedance ZL and the four on-chip resistors R1–R4 lead to incomplete cancellation of the transmit current Itx, which reduces effectiveness of the hybrid system 100. Similarly, mismatches in the frequency response at nodes X and Y lead to high frequency noise, which reduces the performance of the hybrid system 100.
Several schemes have been proposed to address some of the aforementioned deficiencies in various ways. An exemplary approach is disclosed by Moyal, M., Groepl, M., and Blon, T., “A 25-kft, 768-kb/s CMOS Analog Front End for Multiple-Bit-Rate DSL Transceiver,” IEEE Journal of Solid-State Circuits, Vol. 34, No. 12, December 1999, pp. 1961–1972. In this approach, a calibration engine is employed to adjust the impedance at node Y, using a combination of on- and off-chip components. A digital signal processor (DSP) engine driven by a 100% digital echo canceller controls the parameters of these on- and off-components to minimize the effects of bandwidth and resistor matching. However, the output impedance of the digital echo canceller is not calibrated, which means that its return loss is not properly controlled and which means that a poor return loss is likely to result. In addition, this approach requires a 100% digital echo canceller as well as an increased number of package pins to access the off-chip components.
Another approach is disclosed by Tai-Cheng Lee and Behzad Razavi, “A 125-MHz Mixed-Signal Echo Canceller for Gigabit Ethernet on Copper Wire,” IEEE Journal of Solid-State Circuits, Vol. 36, No. 3, March 2001, p. 366. In this approach, the transmit termination and hybrid is located off-chip and slope-matching is not addressed. Other gigabit Ethernet implementations also do not address slope-matching, see, e.g., Roo, P.; Sutardja, S.; Wei, S.; Aram, F.; Cheng, Y., “A CMOS Transceiver Analog Front-End for Gigabit Ethernet over CAT-5 Cables,” Solid-State Circuits Conference, 2001, Digest of Technical Papers, ISSCC, 2001 IEEE International, 5–7 Feb. 2001, pp. 310–311, 458.
Clearly, there is a continuing need in the art for a new hybrid system that is capable of providing outstanding performance without suffering from the aforementioned performance limitations caused by on- and off-chip component imperfections and/or mismatches. The present invention addresses this need.